1. Field of the Invention
This invention relates to improvements in products containing dynamic bits which must be refreshed to maintain data integrity, and more particularly to improvements in refresh circuits and method for using same to reduce standby current and enhance yields of dynamic memory products.
2. Relevant Background
Dynamic memories are constructed to require periodic refreshing of the data contained in the individual cells of the dynamic memory array. The manner by which dynamic memory cells are refreshed is well known in the art. Typically, retention time of a dynamic RAMhas a bimodal distribution. The weak bits typically limit the refresh time and dictate the total refresh frequency and associated refresh current. (Variations in the refresh time which may be required to maintain the contents of a memory cell may arise, for example, due to variations in the manufacturing process in which the cells are constructed, resulting, for instance, in "leaky" memory capacitors, weaknesses in the memory transistor, and so forth.) When these weak bits are addressed independently from the majority of the bits, then the bulk majority of the word lines on a chip can be refreshed at a slower rate. This reduces standby currents by a factor between two to sixteen times, or more. This could have a significant beneficial yield effect on parts with aggressive standby current specifications.
Thus, generally, a refresh cycle for a dynamic memory array is based upon the refresh time required for the weakest cells in the array. That is, if a cell in the array requires a higher refresh frequency than that of the remaining cells in the array, this higher refresh frequency is generally applied to the entire array, and the array refresh specifications are declared to be the shorter refresh time.
Using the shortest time, or weakest bit, to define the refresh time of the array has two salient problems. First, the average speed of the array is decreased, since the memory function of the array cannot be accessed during its refresh. Secondly, the power consumption of the array increases, since the shorter the refresh period, the higher the power that is required to sustain it. The increased power requirements can be an especially important factor in many computer systems in which the dynamic memory components may be used, especially in so-called "laptop" or "notebook" computers, which rely upon batteries to supply their operating power, particularly in a standby mode of operation.
Most prior art solutions involve replacing array rows and columns containing weak bits with redundant rows and columns. The limited number of redundant rows and columns limits the extent to which this can be done to "repair" bad and weak bits. Furthermore, memory arrays are typically divided into subarrays. Often the refresh characteristics of a subarray may be degraded due to local defects affecting this subarray. These degraded subarrays cannot be replaced with standard redundant elements.
Other deficiencies in the prior art are discussed by H. Yamauchi et al., "A Circuit Technology for a Self Refresh 16Mb DRAM with Less than 0.5 .mu.A/mBData Retention Current," IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, November 1995. Yamauchi et al. make reference to the problem of weak bits limiting refresh time. The solution offered by Yamauchi et al. involves changing the cell plate voltages and reference voltages to minimize leakage and allow even bad bits to improve their refresh interval requirements. Yamauchi et al. do not appear to allow for the identification of weak bits or blocks in order to prevent them from limiting the overall chip refresh performance.